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The information presented below was originally printed in the February, March, and April 1993 issues of "Spread Spectrum Scene" magazine (the paper version, before we went online). Minor editorial modifications were made February 2001.


Technical Tricks, February 1993: Correlators

by Randy Roberts, RF/SS Consulting

The real "art" or trade secret technology of Spread Spectrum is in the acquisition and tracking of code phase, carrier frequency and data clock. The only "magic" involved is a practical knowledge of how to do it with correlators. Correlators come in various types:
  • Analog
    • SAW correlator
    • SAW convolver
    • CCD delay line
    • Doubly balanced mixer
  • Digital
    • Full parallel
    • Sliding
    • Hybrid
    • DSP algorithm based
    • AI "smart" correlator

There are plenty of references on correlators and lots of theoretical analyses of how they are supposed to work. However, in the real world it is best to have a favorite circuit or two that has worked well for you in the past and then adapt or modify it for a new application. I will present a few such circuit ideas here.

First, the simplest and quickest correlator to get up and running, by far, is the simple serial, sliding correlator with either two (Tau Dither) or three (Delay Lock/Early-Late) channels, each containing EXOR's or DBM (doubly balanced mixer) correlators. In this approach, one channel is devoted to "on-time" or data channel correlation. In the Tau-Dither two channel system, the second channel is time shared between a slightly "early" and a slightly "late" timing offset channel used to form a "discriminator" function for code tracking purposes. In the three channel system one timing channel is always "early," while the other is always "late." Again a discriminator-like error function is generated to enable code tracking.

To better understand the strategy behind the sliding correlator, assume that the receiver has no knowledge at all of the code phase or frequency to be received. The simplest strategy is just to sequentially try each possible code position until correlation is found. The "data" channel mentioned above is used to detect "code lock," since the signal instantly de-spreads and a narrow band carrier (possibly with data modulation) magically appears when code lock is achieved.

Sliding correlators are simple, reliable and slow! A hybrid, serial/parallel or "pipelined" approach can speed up this type of correlator by a factor of N2, where N is the number of separate, parallel pipelined channels. Thus a 3-way pipelined hybrid sliding correlator, where each parallel pipelined section examines a different section of the code, can acquire sync about 9 times faster than the simple sequential sliding correlator. This is a great return for a nominal addition of circuitry! Today's PLD (Programmable Logic Device) technology makes it easy to implement hybrid sliding correlators up to near the complexity of a full parallel digital correlator.

However, the fastest correlators are fully parallel devices -- they search the entire code epoch length all at once. These devices can use CCDs, SAW (Surface Acoustic Wave) or digital LSI/ASIC technology. SAW convolvers can designed to be programmable for any code -- but the most useful and general purpose parallel correlator is the all-digital device. The chip block diagrams at left and below show some of the available ASIC offerings from Intersil (formerly Harris), TRW and Zilog. Actually Zilog has licensed the SS technology developed by Stanford telecommunications, Inc. for consumer scale commercial development.

The chips shown here are just a sampling of what's available from these and other vendors out there. All three chips shown perform superbly in a correctly interfaced SS system. There is an art to using any of these chips, however. It seems that even to read the data sheets of these chips you need a PhD in microprocessors and silicon BiCMOS technology! Each vendor does make available a certain level of application support -- Stanford Telecom sells evaluation boards and complete development/simulation circuit board subsystems. My recommendation is to select a chip based on the performance you need, build up a simple all-digital test circuit first, then proceed slowly, in small steps, to integrate your new correlator into your SS system. This way you will learn some of the idiosyncrasies of the chip at each step of your design/integration project.

Many companies have spent hundreds of thousands or millions of dollars developing their own full parallel digital correlators. Save your company and your project (as well a your reputation) the time, trouble and expense -- use an existing LSI / ASIC parallel digital correlator chip.

Parallel correlators can sync up in as little as one code epoch (the code repeat time interval). However, noise and statistics usually enter the picture by forcing certain PFA and PD requirements on you. It is thus typical that all digital parallel correlators synch in perhaps 3 to 5 PN code epochs (data bit times). Even this speed is blazingly fast compared to the sliding correlator which syncs up, at best, in the code length's number of data bits.

The use of digital circuitry for correlation provides interesting challenges to the SS innovator -- first it forces him to include both analog and digital circuitry in his design. Next, he must learn something of the rudiments of digital signal processing, if he is to succeed in his efforts. Finally he must learn, by trial of fire and smoke, that SS design is a field for those brave, persevering few who can master multiple technologies and disciplines.

Editor's notes:

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Technical Tricks, March 1993: More About Sliding Correlators

by Randy Roberts, RF/SS Consulting

Last month we talked about DS (Direct Sequence) correlaters in general. We covered an introduction to most of the different types of correlators used today. This month we will concentrate a little on the so called Serial Sliding correlator. This type of analog or digital or analog/digital hybrid implementation is the most commonly used correlator today. It is easy to get working. It is easy to design. It is simple to get working and align. Finally, it is a sure-fire, almost idiot-proof way of correlating a locally generated code against the incoming coded signals.

Key to making this correlator work is that it must be embedded into a multi-channel PN correlation/detection scheme. One way of doing this is shown below in figure 1. In this design a three channel, "Delay Lock" or "Early- Late" correlator design is used. Three time-staggered samples of the PN code are required to make this design work. The time-staggered code samples are easily generated by driving a two or three bit shift register with your locally generated PN code. The actual time stagger used depends on the priorities of your design. It can be any rational fraction of a "chip" -- up to one full chip. Don't make it more than one full chip, however -- it will rapidly loose correlation gain beyond one full chip because of the triangular nature of the PN autocorrelation function. The actual data demodulation is done in the "center" channel. The DC outputs of the "Early" and "Late" channels are subtracted from each other in an Op Amp. The difference between the Early and Late channel correlations forms a straight line, triangulalar-looking, discriminator "S-curve" of the time difference between the local and incoming codes. This DC signal can be filtered and used to close an AFC type tracking loop around the local PN clock source (VCXO or VCO). Thus this correlator architecture is capable of demodulating the data (the de-spreading correlation operation) and generating a time tracking reference signal for the receiver it's used with.

You need more than just the circuitry shown, however! First the initial frequency of the receive PN clock must be offset, by some small amount, from the transmitting PN clock. This frequency offset causes a beat note between the two signals that actually slowly sweeps the received PN timing across the transmitted signal's PN timing. Thus the name "Sliding Correlator." Normally this frequency offset is easy to achieve, because only by a very fortunate accident would the TX and RX PN clocks be on exactly the "right" frequency, and they probably would not stay on the exact same frequency for long anyway.

Next month we'll show you how to control the actual TX and RX frequency offsets precisely, in a fully digital manner. For now, suffice it to say that it is desirable to control the frequency offset between TX and RX PN clock generators! This controlled time offset allows the sliding correlator to sweep precisely through the unknown time delay repetitively so that sync-up time can be controlled.

Authors Note: We never did finish this thread -- I guess we just forgot! But, for those curious few, here are some tips about how to "slide" the local code by the incoming code and thus reliably make a sliding correlator work.

There are two basic schemes to do this digitally (remember the object here is to shift the reference code in controlled increments AND dwell at that code phase long enough to find signal correlation, if it is present!):

  1. Store all possible phase shifts of the code in microprocessor ROM or an outboard E/EE PROM. Then digitally step through all possible reference code phases, dwelling at each at least ONE data bit time (a PN Epoch), thus looking for correlation.

  2. Use what we call an Incremental Phase Modulator (IPM) -- simply use a clock that is 4 to 16 times the chip rate clock for the system digital timing reference in the receiver. Follow this clock with a programmable frequency divider -- e.g., if the clock is 4 x the PN chip rate, use a divide by 3/4/5 counter. In the case of a clock at 8 x the PN chip rate, use a programmable 7/8/9 counter. Make sure this counter is controlled in such a way that it adds or drops only one input clock each time it is adjusted -- this gives us single PN chip phase adjustment capability! Also make sure that the counter can be advanced or retarded only once per data bit time (or one PN Epoch)! This scheme is especially useful in designs using FPGAs or planning to use custom ASICs, because it lends itself to simple, straightforward digital implementation. Note that, by proper design, ONLY advancing OR retarding of the PN chip phase is necessary -- but be careful of long term PN clock oscillator drifts!

Figure 2, below, shows an alternative implementation of the Delay Lock DS loop. This scheme is useful for a DSP based or- more digital demodulation / correlation implementation. The performance of the two block diagrams is identical if the baseband low pass filters of figure 2 match the equivalent bandpass characteristics of the filters in Figure 1.

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Technical Tricks, April 1993: More About Correlators
(A Never Ending Saga?)

by Randy Roberts, RF/SS Consulting

Last month we presented some ideas about delay lock and tau dither circuits for sliding correlators. We also discussed parallel and hybrid digital correlators. This month we will discuss some correlation basics and show some detailed issues that must be addressed when implementing correlators. We also hint at how to build that "nifty" hybrid digital correlator.

The basic definition of mathematical correlation is the integral:

Don Lancaster in the August 1992 issue of Electronics Now showed that correlation can be performed in the three different ways, as shown in Figures 1 and 2.

One of the problems inherent in the implementation of digital correlator circuitry is that the correlator's ideal triangular shape usually gets digitized as shown in Figure 3.

Another real world problem is time sidelobes and poor choices of PN codes. Figure 4 shows what these can look like.

So now you know some of the real world limitations of correlators. You may ask -- how bad are these effects??! You may also ask -- are there other effects that must be accounted for? The answers to these questions are not a simple yes or no. First, you may need to model all the imperfections, quantization errors, noise and code effects before you really know how bad they are. Second, other imperfections can creep into your design. The foremost among these other problems is the effect of bandlimiting on the shape of the correlation triangle. In most cases, some RF or IF bandpass filtering is used in any real world transmitter or receiver. This rounds out the peak of the correlation triangle, loses a little correlation gain and spreads out / rounds out the sharp corners of the correlation function near the baseline. Other problems to watch out for are in-chip multipath signals and intersymbol interference.

All this sounds complicated, doesn't it? Well that's part of what keeps us SS consultants busy. It's not really so bad if you use communications block diagram analysis and system modeling tools. TESLA is a PC based tool widely used for- electronic system modeling and optimization. COMDISCO has an expensive, workstation-based package that does everything but wash the dishes. It is a super package, but it costs an arm and a leg!

Figure 5 shows how to build an analog "parallel" correlator. You might use a SAW device or a CCD shift register for this scheme. It is essentially an analog perfectly matched filter- for the PN code being transmitted. The output sum can be fed to a threshold circuit (a comparator) to mark the time occurrence of synchronization. Once correlation sync is obtained, the tracking function (delay lock or tau-dither) can be initiated and you are now ready to demodulate the data that follows the unmodulated "sync preamble."

An all-digital, baseband version of the "matched filter" correlation detector is shown in figure 6. This scheme is also implemented at baseband and is a practical scheme that can be used for real world SS communications. Specifically, this correlation should be done on I and Q (quadrature) components of the receiver's IF. This requires sampling the IF signal at a rate equal to, or above, the PN clock.

See how you might do that hybrid correlator yet?

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