What's New

Part 1

Spring 96 (April 29)

[Encryption for ISDN BRI] [SSS Online] [New Products -- PCS Market Report] [New Products -- AMI]
[New Products -- STEL] [DS versus FH?] [All About Correlators] [Past What's New Pages]


New Products


Source:Data TeleMark L.C.
March 29, 1996, 8201 Greensboro Dr., Suite 1000 McLean, Virginia, 22102 USA ISDN... wherever you want it!

Contact: Gary Koelsch (703) 847-5475, gkoelsch@datatelemark.com

DTM To Provide Secure ISDN Communications With New Encryption Device

Data TeleMark L.C. (DTM America) is pleased to announce the first "off the shelf" encryption device for ISDN Basic Rate Interfaces.

This product, called D.I.C.A. 7800, will be introduced at TechNet '96, June 4 - 6 in Washington D.C. The device allows user to encrypt the contents of the B-channels of an ISDN Basic Rate Interface for any application and any network standard worldwide.

"Security in communications is a major issue. The advantages of this product are obvious," said Data TeleMark's President Frank Piepiorra. "We expect a large response from all current users of ISDN but we also think that encryption will encourage others to deploy ISDN more widely." Piepiorra also added.

D.I.C.A. 7800 uses the most powerful cryptographic techniques available. The main key combinations are based on symmetric cryptographic algorithm. For each ISDN call a new traffic key, different for each B-channel, will be allocated. The current key sizes are based on FEAL 16 X or Data TeleMark's own 32 bit DCA32 algorithm. A tool kit will also be available that allows users to implement other customized or existing encryption a lgorithm.

The device has two ISDN BRI ports, one which will be connected to the ISDN network and the other to the application. There is no need for reconfiguration at the users or network side. The device will detect automatically whether the called party supports encryption.

Data TeleMark's mission is to provide equipment and consulting to get ISDN to any place worldwide. DTM's D.I.C.A. product line extends ISDN over "non-ISDN" links such as satellites, radio or digital cables and can be combined now with encryption. The company has provided and supported such products since 1994.

For more information please refer to DTM's World Wide Web home page at: Data TeleMark, L.C.


SSS Online is Growing and Adding New Features!


Source: Randy Roberts, Editor & Publisher of SSS on-line magazine.
March 25, 1996, El Granada, CA.

Spread Spectrum Scene Online is continuing to grow and expand. In the last two weeks, alone, we have added a "Weekly Feature" and a new "Spotlight" section to our menu. To better serve our readers / visitors we also have added "Classified Ads" and "JOBS!" pages.

Please check out these new topics, if you haven't already tried them!

In our first three months on the WEB we continually increased our hit rate from something like 10 or 12 per day, in January, to over 200 per day -- over the last weekend. It seems that some of you are starting to notice us. While we are not trying to be Popular and win any top 5% awards -- we are happy that more of you out there in "HyperLand" are showing up here occaisionally.

Our goal is provide information that you want and need about Wireless and SS technology. We want to be the Internet "clearinghouse" for technical information and useful, informative links to other interesting technical sites. As part of our "giving back" to the 'Net we additionally provide information and links to many "Hot Sites" and link a lot of interesting, fun stuff for a general audience. If you would like to suggest new links to us, just send us email with your sugestions.

In the next three months we look forward to updating this site with even more information and we will probably break down and join the JAVA bandwagon -- we will be experimenting with new Home Page formats! Keep coming back to see what's up here! We'll try to keep you informed and amused.

For more information

See contact information below!


New Products -- New Report


MOUNTAIN VIEW, CA - The emerging market for cellular and personal communication systems transmission equipment will exceed $10 billion per year by 2000, according to a new market study from Silicon Valley technology research firm Strategies Unlimited. Annual demand for cellular and PCS base stations and microwave back-haul links is forecast to grow from $5.9 billion in 1996 to over $10.2 billion in the year 2000.

Telecommunications operators spent over $8 billion in last year's U.S. Federal Communications Commission auction to obtain PCS (Personal Communication Systems) licenses, in anticipation of PCS becoming the next standard in wireless telephones. The study predicts that the market will make the transition from cellular to PCS in two stages. From 1996 through 1998, the market standard is expected to shift from analog to digital cellular, with PCS introduced only in select markets. After 1998, PCS market share is forecast to grow rapidly in North America, Europe and southeast Asia.

Digital cellular subscribers currently represent 19% of the world market. That share is expected to grow to 45% by 2000. Market demand for RF subsystems and components in 800 MHz digital cellular systems is expected to grow over 30% per year from 1994 through 2000.

PCS is not expected to penetrate 1% of the global wireless telephone market until 2002. The only two PCS networks currently available in the U.S. are in the Baltimore-Washington corridor through American Personal Communications operating as Sprint Spectrum, and in Hawaii operated by Western Wireless Corporation. San Diego is expected to be the nation's next PCS market, with Pacific Bell Mobile Services announcing plans to have a PCS network up prior to the Republican National Convention this summer. PCS service providers who won U.S. licenses in the FCC auction are required to have their networks up and running by 1997.

Annual base station equipment sales are expected to reach $5.3 billion in 2000. PCS base station equipment sales are forecast to grow to $1 billion in 2000. Market demand for RF subsystems and components within PCS services is expected to grow 82% per year over the next five years.

PCS provides a cost and technology advantage over cellular systems by offering more capacity per cell site. The cost-effective infrastructure of PCS is expected to push down the costs of wireless telephone service dramatically. By 2000, service costs for new PCS subscribers will drop to approximately one-third the cost of today's cellular service.

The market study provides an in-depth analysis and five-year forecast of worldwide cellular and PCS services by region and technology. Annual market estimates for analog cellular, digital cellular (TDMA, CDMA, GSM, PDC) and PCS (DCS 1800/PCS 1900) are provided for six world regions from 1996 through 2000. The study also profiles the world's leading manufacturers of cellular and PCS technology, provides a summary of PCS service operators and their assigned territories, and analyzes the regional market dynamics that will drive cellular and PCS service growth over the next five years.

The 348-page study entitled RF Components for PCS Base Stations and Links - A Market Review and Forecast 1995-2000, includes over 300 illustrations and 140 tables. The study is available for $2,950 if ordered before April 15, 1996; thereafter, the report will sell for $3,450.

For the past 16 years, Strategies Unlimited has served as an international market research and consulting fi rm to hi gh-tech industries in wireless communication, optoelectronics and photovoltaics.

For more information, Contact:

Dr. George Bechtel
Director, Wireless Division
Strategies Unlimited
201 San Antonio Circle
Mountain View, CA 94040
TEL: 650-941-3438
FAX: 650-941-5120
email: strtultd@ix.netcom.com


New Products


Targets Telecom and Datacom Markets

POCATELLO, Idaho -- March 25, 1996 -- American Microsystems, Inc. (AMI) announced the formation of its Multichip Products Division (MPD) to address the growing demand for multichip modules (MCM) in the datacom and telecom markets.

The newly established AMI division provides a full range of services from concept to design, to modeling, to assembly and test. A wide variety of substrates, and bonding techniques are offered.

"Our view of Multichip Products," said Randy Cook, vice president of AMI's Multichip Products Division, "is that of multiple ICs combined with discrete components integrated on a single substrate. For example, a MCM may combine as many as 13 ICs and 100 discrete components on a 2"x2" substrate."

Multichip products are growing in popularity. They have an obvious attraction: they take up dramatically less circuit board real estate and often provide increased performance. There are three additional benefits: one, lower system costs when complex portions of a system are integrated into a multichip; two, easier diagnostics and simpler upgrading, and three, a low-risk approach to integration.

Until recently, cost and testability have been legitimate concerns about MCMs. However, technology advances have increased yields to the point that MCMs meet the budget requirements for many applications, especially in the telecommunications and datacom arenas.

The formation of MPD will allow AMI customers, including present ASIC customers, to take advantage of its multichip expertise. AMI has been designing, manufacturing, and testing digital ASICs and mixed-signal ICs for 30 years. It has the equipment and expertise to transfer ASIC test methodologies to multichip products.

"The decision to move to an MCM is not an easy one," according to Randy Cook. "But once the decision is made, the customer has a better chance of success with AMI for three reasons. One, if we did the ASIC we can test it before assembly into the MCM. Two, we can offer any of the substrates and assembly technology. Finally, we can develop electrical tests in cooperation with the customer to facilitate complete turnkey deliveries."

MPD works with strategic partners from around the world for the final manufacturing of the multichip product. These technology partners must maintain the ISO 9002 certification, as AMI does.

AMI is a leader in application specific solutions through superior semiconductor design and manufacturing processes. The company, based in Pocatello, Idaho, provides a full range of digital and mixed-signal ASICs, CMOS foundry services, application-specific standard products, and high- level integrated solutions through multichip products.

For more information, Contact:

Mr. Randy Cook
American Microsystems, Inc.
2300 Buckskin Road
Pocatello, Idaho 83201
TEL: 208-233-4690
email: cook@poci.amis.com


New Products


Sunnyvale, CA -- February 26, 1996 -- Stanford Telecommunications, Inc. Telecom Component Products Group announced today the availability of a new modulator chip for hybrid fiber/coax (HFC) CATV networks. Designated the STEL-1108, the new chip is a key component in the transmission of digital video, telephone, and data from subscriber premises (homes, businesses, etc.) to CATV headend equipment.

Building on the success of the previously issued STEL-1103 and incorporating improvements based on customer feedback, the STEL-1108 provides better performance in clock rate, duty cycle, and burst capability, along with lower Power consumption. Among other improvements, the STEL-1108 can operate in continuous mode, allowing use for both burst and point-to-point systems.

The Stanford Telecom STEL-1108 is a complete QPSK modulator on a single chip that features clock speeds up to 126 MHz. It operates at up to 12.6 Mbps in QPSK mode. A 12~ MHz Quadrature NCO provides digitally modulated carriers from D.C. to 50 MHz continuous mode, which simplifies upconversion of signals to higher frequencies. The device incorporates dual 32-TAP FIR filters that are programmable for digital spectral shaping, and interpolation filters that eliminate unwanted alias energy. In addition, the STEL-1108 can operate in either burst or continuous mode. The device is contained in an 80-Pin PQFP surface mount package. The STEL-1108 uses 3.3 V CMOS technology for low-power applications such as line-powered, side-of- the-house network interface units. The STEL-1108 is ideally suited to applications where precise spectral shaping and fine resolution tuning over 50 MHz are required.

Chuck Frank, Managing Director for the Telecom Components Products Group states that, "The addition of the STEL-1108 to our Product family rounds out our current line of digital ASICs and assemblies for HFC networks and reinforces Stanford Telecom's commitment to the CATV industry."

To address this, Stanford Telecom has developed a series of Applications Specific Integrated Circuits (ASICs) and assemblies that are integrated within subscriber terminals or set-top boxes and headend equipment to Perform the necessary digital signal processing to send data from the subscriber and receive it at the headend.

The STEL-1108 is available in volume production at less than $20 each. Delivery quantities from 1 to 5 are available from stock. Production quantities are available 12 to 14 weeks A.R.O.

Stanford Telecom designs, manufactures and markets advanced digital telecommunications products and systems to establish or enhance communications via satellites, terrestrial wireless and cable. The Company also provides communication systems networking solutions and GPS navigation products.

Stanford Telecom'sexpertise encompasses all the technologies required for these systems including radio frequency (RF), spread spectrum, waveform, coding, modem, ASIC, software and system design. The Company maintains a low cost commercial manufacturing capability and offers cost effective engineering services.

Historically, CATV systems have been largely used for one-way distribution of video channels, with great amounts of data moving from the central cable facility (headend) to the subscriber, and very little information going the other way~ With the rapidly growing market for interactive voice/data/video, there is a new demand for increased communication in both directions. Accommodating this increasing flow of data within existing CATV hybrid fiber/coax networks requires the use of digital techniques that work within the existing bandwidth limitations while imposing less limitation in capacity than conventional analog techniques.

For more information, Contact:

Mr. William Patton
Stanford Telecom
1221 Crossman Avenue
Sunnyvale, CA 94089-1117
TEL: 408-745-0818
FAX: 408-745-7756
email: Bill_Patton@ccmail.stelhq.com



Which is Better, Direct Sequence (DS) or Frequency Hop (FH) Spread Spectrum?

This information is re-printed from "Spread Spectrum Scene" magazine (paper version), Volume 3, Number 3, page 8.

This frequently asked question is really rather hard to answer. There is no real unbiased way to compare today's crop of commercial direct sequence radios to the frequency hoppers that are available. Sure, claims and counter claims abound, but the truth is hard to find.

Why? A little history helps explain what has evolved in the commercial SS world. First of all, the FCC's first Part 15 rules (published in 1989), did not require any SS radio to have processing gain - nor did these initial rules differentiate between fast and slow hopping. Thus the earliest SS radios produced, could use almost anything as long as they met the then defined Part 15 rules.

Some of these early radios used post detection correlation and thus, were not "TRUE DIRECT SEQUENCE" radios, at all. Only when correlation is done before detection, can all of the anti-jam and anti-interference benefits of direct sequence be seen. Some of the early hoppers changed frequency so slowly that they transmitted tens of thousands of bits on a single frequency dwell (and made no provision for error detection - let alone correction).

It's no wonder then, that some of these early radios (of either variety) were very short of the long hyped interference immunity that they were supposed to have. In fact, in Europe and the United Kingdom, Direct Sequence has gotten such a bad name from early trials with overly simple Direct Sequence radios, that frequency hoppers have almost become a standard.

The FCC tried to rectify this situation in 1992, with new Part 15 technical rules that require a minimum processing gain and better definitions of hopping speed and numbers of hopping channels required. But, out of intense lobbying efforts, came "grandfather provisions" that allowed existing approved designs to be sold for 5 years beyond 1989. The most recent actions of the FCC, however, have granted "dispensations" to those "grandfathered" manufacturers who yelled the loudest. The "deal" that was struck allows slow hoppers and post detection correlation (Non-TRUE DIRECT SEQUENCE) radios to continue to be sold if they keep their power output below 100 milliwatts.

So if a manufacturer cannot furnish a radio with significantly more power than 100 mW, they are probably peddling an old, inferior design - Caveat Emptor!

So the answer to the which is better is still unclear -- neither is any good, if it's an old design! Fast hoppers (no more than a few bits per frequency dwell) can have almost identical performance to Direct Sequence, but we don't know of any commercial radios that hop that fast!

Real (or TRUE) DS and FH radios can each be vulnerable to certain kinds of interference. No one modulation is best against any and ail interferers! However, the best that can be done with SS, is to use a hybrid, or combination of DS and FH, that adapts to channel conditions in real time. The BEST SS modulation is thus seen to be not either DS or FH -- but both, when used optimally against adverse interference, multipath and channel conditions.

It's too bad that the FCC does not allow "smart" adaptive hybrid modulations yet, under Part 15!

NOTE: The latest FCC NRPM (Docket 96-8) does include a provision for limited "smart hopping," see FCC News.



All About Correlators

This information is re-printed from "Spread Spectrum Scene" (paper version)Technical Tricks February, 1993

The real "art" or trade secret technology of Spread Spectrum is in the acquisition and tracking of code phase, carrier frequency and data clock. The only "magic" involved is a practical knowledge of how to do it with correlators. Correlators come in various types:

  • SAW correlator
  • SAW convolver
  • CCD delay line
  • Doubly balanced mixer
  • Full parallel
  • Sliding
  • Hybrid
  • DSP algorithm based
  • AI "smart" correlator

There are plenty of references on correlators and lots of theoretical analysis of how they are supposed to work. However, in the real world it is best to have a favorite circuit or two that has worked well for you in the past and then adapt or modify it for a new application. I will present a few such circuit ideas here.

First, the simplest and quickest correlator to get up and running, by far, is the simple serial, sliding correlator with either two (Tau Dither) or three (Delay Lock/Early-Late) channels, each containing EXOR's or DBM (doubly balanced mixer) correlators. In this approach, one channel is devoted to "on-time" or data channel correlation. In the Tau-Dither, two channel system, the second channel is time shared between a slightly "early" and a slightly "late" timing offset channel used to form a "discriminator" function for code tracking purposes. In the three channel system one timing channel is always "early," while the other is always "late." Again a discriminator-like error function is generated to enable code tracking.

To better understand the strategy behind the sliding correlator, assume that the receiver has no knowledge of the code phase or frequency to be received, at all. The simplest strategy is just to sequentially try each possible code position, until correlation is found. The "data" channel, mentioned above, is used to detect "code lock," since the signal instantly de-spreads and a narrow band carrier (possibly with data modulation) magically appears when code lock is achieved.

Sliding correlators are simple, reliable and slow! A hybrid, serial/parallel or "pipelined" approach can speed up this type of correlator by a factor of N2 , where N is the number of separate, parallel pipelined channels. Thus a 3 way pipelined hybrid sliding correlator, where each parallel pipelined section examines a different section of the code, can acquire sync about 9 times faster than the simple sequential, sliding correlator. A great return for a nominal addition of circuitry. Today's PLD (Programmable Logic Device) technology makes it easy to implement hybrid sliding correlators up to near the complexity of a full parallel digital correlator.

However, the fastest correlators are fully parallel devices -- they search the entire code epoch length all at once. These devices can use CCDs, SAW (Surface Acoustic Wave) or digital LSI/ASIC technology. SAW convolvers can designed to be programmable for any code -- but, the most useful and general purpose parallel correlator is the all digital device. The chip block diagrams at left and below show some of the available ASIC offerings from Harris, TRW and Zilog. Actually Zilog has licensed the SS technology developed by Stanford telecommunications, Inc. for consumer scale commercial development.

The chips shown here are just a sampling of what's available from these and other vendors out there. All three chips shown perform superbly in a correctly interfaced SS system. There is an art to using any of these chips, however. It seems that to even read the data sheets of these chips you need a PhD in microprocessors and silicon BiCMOS technology. Each vendor does make available a certain level of application support -- Stanford Telecom sells evaluation boards and complete development/simulation circuit board subsystems. My recommendation is to select a chip based on the performance you need, build up a simple all digital test circuit first, then proceed slowly, in small steps, to integrate your new correlator into your SS system. This way you will learn some of the idiosyncrasies of the chip at each step of your design/integration project.

Many companies have spent hundreds of thousands or millions of dollars developing their own full parallel digital correlators. Save your company and your project (as well a your reputation) the time, trouble and expense -- use an existing LSI / ASIC parallel digital correlator chip.

Parallel correlators can sync up in as little as one code epoch (the code repeat time interval). However, noise and statistics usually enter the picture by forcing certain PFA and PD requirements on you. It is thus typical that all digital parallel correlators synch in perhaps 3 to 5 PN code epochs (data bit times). Even this speed is blazingly fast compared to the sliding correlator which syncs up, at best, in the code length's number of data bits.

The use of digital circuitry for correlation provides interesting challenges to the SS innovator -- first it forces him to include analog and digital circuitry both in his design. Next, he must learn something of the rudiments of Digital Signal Processing, if he is to succeed in his efforts. Finally he must learn, by trial of fire and smoke, that SS design is field for those brave, persevering few, who can master multiple technologies and disciplines.

Technical Tricks, March 1993

More About Sliding Correlalors

Last month we talked about DS (Direct Sequence) correlaters in general. We covered an introduction to most of the different types of correlators used today. This month we will concentrate a little on the so called Serial Sliding correlator. This type of analog or digital or analog/digital hybrid implementation is the most commonly used correlator today. It is easy to get working. It is easy to design. It is simple to get working and align. Finally, it is a sure-fire, almost idiot-proof way of correlating a locally generated code against the incoming coded signals.

Key to making this correlator work is that it must be embedded into a multi-channel PN correlation/detection scheme. One way of doing this is shown below in figure 1. In this design a three channel, "Delay Lock" or "Early- Late" correlator design is used. Three time staggered samples of the PN code are required to make this design work. The time staggered code samples are easily generated by driving a two or three bit shift register with your locally generated PN code. The actual time stagger used depends on the priorities of your design. It can be any rational fraction of a "chip" -- up to one full chip. Don't make it more than one full chip, however -- it will rapidly loose correlation gain beyond one full chip because of the triangular nature of the PN autocorrelation function. The actual data demodulation is done in the "center" channel. The DC outputs of the "Early" and "Late" channels are subtracted from each other in an Op Amp. The difference between the Early and Late channel correlations forms a straight line, triangulalar looking, discriminator "S-curve" of the time difference between the local and incoming codes. This DC signal can be filtered and used to close an AFC type tracking loop around the local PN clock source (VCXO or VCO). Thus this correlator architecture is capable of demodulating the data (the de-spreading correlation operation) and generating a time tracking reference signal for the receiver it's used with.

You need more than just the circuitry shown, however! First the initial frequency of the receive PN clock must be offset, by some small amount, from the transmitting PN clock. This frequency offset causes a beat note between the two signals that actually slowly sweeps the received PN timing across the transmitted signal's PN timing. Thus the name "Sliding Correlator." Normally this frequency offset is easy to achieve, because only by a very fortunate accident would the TX and RX PN clocks be on exactly the "right" frequency they probably would not stay on the exact same frequency for long anyway.

Next month we'll show you how to control the actual TX and RX frequency offsets precisely, in a fully digital manner. For now, Suffice it to say that it is desirable to control the frequency offset between TX and RX PN clock generators! This controlled time offset allows the sliding correlator to precisely sweep through the unknown time delay repetitively so that sync-up time can be controlled.

Editors Note: We never did finish this thread -- I guess we just forgot! But, for those curious few, here are some tips about how to "slide" the local code by the incoming code and thus reliably make a sliding correlator work.

There are two basic schemes to do this digitally (remember the object here is shift the reference code in controlled increments AND dwell at that code phase long enough to find signal correlation, if it is present!):

(1) Store all possible phase shifts of the code in microprocessor ROM or an outboard E/EE PROM. Then digitally step through all possible reference code phases, dwelling at each at least ONE data bit time (a PN Epoch), thus looking for correlation.

(2) Use what we call an Incremental Phase Modulator (IPM) -- simply use a clock that is 4 to 16 times the chip rate clock for the system digital timing reference in the receiver. Follow this clock with a programmable frequency divider, e.g. if the clock is 4 x the PN chip rate, use a divide by 3/4/5 counter. In the case of a clock at 8 x the PN chip rate, use a programmable 7/8/9 counter. Make sure this counter is controlled in such a way that it adds or drops only one input clock each time it is adjusted -- this gives us single PN chip phase adjustment capability! Also make sure that the counter can be advanced or retarded only once per data bit time (or one PN Epoch)! This scheme is especially useful in designs using FPGAs or planning to use custom ASICs, because it lends itself to simple, straightforward digital implementation. Note that, by proper design, ONLY advancing OR retarding of the PN chip phase is necessary -- but be careful of long term PN clock oscillator drifts!

Figure 2, below, shows an alternative implementation of the Delay Lock DS loop. This scheme is useful for a DSP based or- more digital demodulation / correlation implementation. The performance of the two block diagrams is identical if the baseband low pass filters of figure 2 match the equivalent bandpass characteristics of the filters in figure 1.

Technical Tricks, April 1993

About Correlators (A Never Ending Saga?)

Last month we presented some ideas about delay lock and tau dither circuits for sliding correlators. We also discussed parallel and hybrid digital correlators. This month we will discuss some correlation basics and show some detailed issues that must be addressed when implementing correlators. We also hint at how to build that "nifty" hybrid digital correlator.

The basic definition of mathematical correlation is the integral :

Don Lancaster in the August 1992 issue of Electronics Now showed that correlation can be performed in the three different ways shown in figures 1 and 2.

One of the problems inherent in the implementation of digital correlator circuitry, is that the correlator's ideal triangular shape usually gets digitized as shown in figure 3.

Another real world problem is time sidelobes and poor choices of PN codes. Figure 4 shows what these can look like.

So now you know some of the real world limitations of correlators. You may ask -- how bad are these effects'! You may also ask -- are there other effects that must be accounted for? The answers to these questions are not a simple yes or no. First, you may need to model all the imperfections, quantization errors, noise and code effects before you really know how bad they are. Second, other imperfections can creep into your design. The foremost among these other effects is the effect of bandlimiting on the shape of the correlation triangle. In most cases, some RF or IF bandpass filtering is used in any real world transmitter or receiver. This rounds out the peak of the correlation triangle, loses a little correlation gain and spreads out / rounds out the sharp corners of the correlation function near the baseline. Other problems to watch out for are in-chip multipath signals and intersymbol interference.

All this sounds complicated -- doesn't it? Well that's part of what keeps us SS consultants busy. It's not really so bad if you communications block diagram analysis and system modeling tools. TESLA is a PC based tool widely used for- electronic system modeling and optimization. COMDISCO has an expensive, workstation-based package that does everything but wash the dishes. It is a super package, but it costs an al-m and a leg!

Figure 5 shows how to build an analog "parallel" correlator. You might use a SAW device or a CCD shift register for this scheme. It is essentially an analog perfectly matched filter- for the PN code being transmitted. The output sum can be fed to a threshold circuit (a comparator) to mark the time occurrence of synchronization. Once correlation sync is obtained, the tracking function (delay lock or tau-dither) can be initiated and you are now ready to demodulate the data that follows the unmodulated "sync preamble."

An all-digital, baseband version of the "matched filter" correlation detector is shown in figure 6. This scheme is also implemented at baseband and practical scheme that can be used for real world SS communications. Specifically, this correlation should be done on I and Q (quadrature) components of the receiver's IF. This requires sampling the IF signal at a rate equal to, or above, the PN clock.

See how you might do that hybrid correlator yet?

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