Voice Link Over Spread Spectrum Radio -- Part 2
by James Vincent, G1PVZ
Editor's Note: We proudly present the second and final installment of James
Vincent's article, which is reprinted from the October 1993 issue of ELECTRONICS
+ WIRELESS WORLD. In this installment, James presents the details of this design
with schematics, technical descriptions and references. However, due to
complicated copyright issues, we are not able to post the
figures for this article online. To obtain a copy of the complete article or just
the figures -- please contact Mr. Vincent directly by email:
Pseudo-random codes can be categorized as being linear or non-linear codes. Linear codes are generated using linear operations (which for binary pseudo-random codes is solely modulo-2 addition or subtraction). This essentially means only ex-OR gates are used in the shift register feedback path. A pseudo-random generator which does not use such techniques is termed non-linear.
The most commonly used group of pseudo-random sequences used in spread spectrum are the maximal linear code sequences (sometimes called M-sequences or PN, pseudo-noise, codes). Maximal codes are the longest codes that a shift register of specified length can produce and have mathematical properties well suited to spread spectrum communications (SSS Note: other codes such as GOLD or KASAMI codes can provide better CDMA performance than the maximal codes).
A maximal shift register pseudo-random generator consists of a shift register with selected outputs being exclusive -ORed and fed back into the shift register input. The circuit goes through a number of states (determined by the bits in the shift register at each clock pulse) before it repeats itself after a set number of states for a shift register of length m is 2m, ie for a 7-stage shift register 27=128 states. However the all-zero state is not allowable as the pseudo-random generator would lock-up as ex-ORing two logic 0 results in yet another logic 0 at that input. Therefore a maximal length pseudo-random sequence 2m-1 bits long before repeating itself.
To obtain a maximal sequence, the correct shift register outputs (tap points) must be found. these could be found by experimentation but this would be very time consuming! However tables of feedback connections are available3.
Maximal codes are the longest codes that a shift register of specified length can produce and have mathematical properties well suited to spread spectrum communications.
A 7-stage (i.e. seven flip-flop) shift register can produce a maximal code of length 27-1=127 bits (known as chips in spread spectrum terminology) long. The feedback tap points may be taken from the following stages:
As the simplest circuit implementation is often desire, the first option of tapping the seventh and first stages is selected.
To avoid the all-zero lock up problem, inverting stages are inserted before the shift register input and at the output of the shift register input and at the output of the shift register. When the shift register is switched on, a reset pulse is initiated. This pulse initiates all shift register outputs to logic 0. This would normally lock up the pseudo-random sequence generator. However the input inverter injects a logic 1 so that the maximal sequence can commence. The output inverter ensures that maximal code output is inverted negating the effect of the anti-lock-up inverter at the input. The maximal code is also available at the output (A) of the modulo-2 adder, but the second inverter output is normally used to permit direct drive of the DBM in a direct sequence system.
Receiver Functional Description
The 435 MHz direct sequence (DS) signal is first amplified by a low noise amplifier2 followed by a helical filter and further amplification by a low noise amplifier block (MANILN) and a MAR8 (SSS Note: Be careful with the MAR-8, it is not unconditionally stable -- two lower gain MARs might work better than the MAR-8 in this application). The DS signal is mixed with a 7dBm 365 MHz local oscillator in a down-converter. The DS signal now centered on an intermediate frequency of 70 MHz is amplified (MAR8) and bandpass filtered (PIF-70), before being resistively split into three identical signal paths. In each signal path (late, on time or early) the 70 MHz signal is amplified by a further MAR6 amplifier. A DBM configured as a biphase shift keyer is driven by and early, on time or late pn code. The DBM is buffered by 50 ohm pads and driven by an AC logic buffer as with the DBM used as a BPSK modulator in the transmitter.
Assuming synchronism the de-spread output is injected into a NE605 low power FM IF integrated circuit. The second local oscillator at 64 MHz in conjunction with the on-chip mixer downconverts the despread signal (which contains the data in a BPSK format) to 6 MHz. The NE605 further amplifies the 6MHz signal and provides filtering using 6MHz ceramic filters originally designed for television sound strips.
A RSSI (received signal strength indicator) is available from each NE605 with a 90 dB range logarithmic output. The RSSI outputs from the early and late channels go to the delay locked loop circuit. The despread data output from the on time (punctual) channel is further amplified by a MAR8 amplifier before being frequency doubled in a Mini Circuits RK3 doubler. As previously discussed the de-spread data signal has a biphase shift keyed (BPSK) format. The BPSK frequency spectra is similar to that of a double sideband suppressed carrier and as for DSBSC, carrier recovery is required to demodulate the signal. It can be shown mathematically3 that by squaring or doubling a BPSK signal a twice frequency carrier is obtained. After passing the doubled signal though a 12 MHz crystal used as an exceptionally narrow bandpass filter, the signal is applied to a synchronous oscillator. This circuit (see section on The Synchronous Oscillator) free runs at 5 MHz and on application of the 12 MHz signal synchronously locks to half of the inut frequency. This locked 5 MHz output if buffered and amplified to produce a logic level 0 / +5 V output, which together with the signal from the ontime (punctual NE605 IC is injected into a DBM configured as a phase detector. The voltage output of the phase detector is amplified, level shifted and using a voltage comparator, converted into standard logic levels.
The output form this squaring loop BPSK demodulator does not recover the original data polarity as the original phase of the signal is lost in the (frequency) doubling process. This is why the data was diphase encoded at the transmitter so that the correct data polarity could be recovered at the receiver.
An edge detector configured from exclusive-OR gates produces a negative pulse for both positive and negative edges of the comparator's diphase data stream output. The edge detector output triggers monostable A, one half of a dual monostable. (Note: all monostables are not retriggerable). Monostable A is set to produce a positive output pulse with a duration of 75% of the diphase bit cell period. The Q output of monostable A triggers monostable B which produces a positive output pulse of duration 25% of the diphase bit cell period. It turn the negative edge of monostable B output triggers monostable C which produces a positive pulse with a duration of 50% of the diphase bit cell period. D-type flip-flop D1 is clocked by the /Q output of monostable C and flip-flop D2 by the Q output.
The positive edges of the Q and /Q outputs of monostable C occur before and after any mid-bit transition. Thus when D1 and D2 are clocked, their outputs will be different if the diphase encoded bit represents a one, or the same if the diphase encoded bit represent a zero. If D1 and D2 outputs are exclu sive ORed then the instantaneous NRZ data is obtained. The clock is recovered at the Q output of monostable A. It can be seen that missing or corrupted disphase data could cause monostable A to trigger on a mid-bit transition rather than a "start' transition. This false synchronization will be corrected on the next diphase encoded zero as monostable A will not be triggered.
The recovered clock and NRZ data is delivered to the delta modulator integrated circuit where it is converted back into audio and amplified to a loudspeaker. The delay lock loop and code correlation, synchronization and tracking. The difference amplifier is followed by a summing amplifier used to adjust the quiescent frequency of the voltage controlled crystal oscillator and a low pass filter. The output of the inverter drives the control input of the voltage controlled oscillator (VCXO). The VCXO consists of a high stability AT cut crystal in a discrete transistor based oscillator with varicap frequency control. The oscillator's low voltage output is amplified by approximately 10,000 with a linear biased HC logic gate. This hard limits the buffer's output to standard logic levels. the VCXO provides a highly stable, repeatable output which has a 2 kHz tuning range centered on 8 MHz for a tuning voltage of 0 to 6 VDC.
The VCXO output is divided by two to produce a 4 MHz clock. This clock signal drives the 127 chip maximal PN generator. The output of this PN generator is re-clocked through a shift register by the original 8 MHz clock. By extracting the three outputs from neighboring outputs three identical PN codes are available (early, on-time and late) but with a half clock cycle difference between them. Thus the early code is one clock cycle (or "chip" in spread spectrum terminology) ahead of the late code. Each PN code generator output drives the relevant correlator (de-spreader). Se section Delay Locked Loop.
In operation the VCXO is offset to s slightly higher frequency than the crystal clock in the transmitter, effectively producing a sliding correlator. Assuming that the receiver is in range and unsynchronized, the receiver code will slide past the transmitter code. At one point in time the two codes will match. This will result in correlation and the direct sequence signal will be de-spread. The early channel will be despread before the late channel and the early RSSI value will be considerably higher than the late uncorrelated channel. this difference signal after filtering steers the VCXO output toward the frequency of the transmitter clock. When the receiver and the transmittter clocks and PN codes are synchronized the RSSI outputs from the early and late channels will be identical and the difference amplifier output will be zero. Should the receiver clock be retarded greater energy will be present in the late channel than the early channel, and the VCXO will be driven by the difference amplifier to increase its frequency. If the receiver clock is advanced greater energy will be in the early channel than the late channel and the VCXO will be driven by the difference amplifier to decrease its frequency. Thus the delay locked loop will maintain synchronism once the sliding correlator has caused the receiver to lock. The frequency offset is selected such that it will cause rapid synchronization but remain within the capture range of the loop.
Construction and Testing
The direct sequence transmitter and receiver were constructed on a combination of Veroboard and double-sided printed circuit boards. The radio frequency circuits were built on the double-sided PCBs, with the usual RF design techniques employed. The photograph of the completed transmitter-exciter and receiver shows the combination of construction techniques used.
The system is designed around easily obtainable components and all inductors and filters are selected from either the Toko or Mini-Circuits range to avoid the difficulties of winding coils.
The set-up of the receiver requires a functioning exciter as a source of a direct sequence signal, hence the exciter is adjusted first. This involves setting the master 4 MHz crystal oscillator with the aid of a frequency counter. How the receiver can be directly connected (with a suitable attenuator in-line to prevent overload) to the exciter output. Initially, the 64 MHz second local oscillator should be adjusted on frequency. The VCXO's frequency is set using the center frequency adjust potentiometer, to be slightly higher or lower than twice the measured frequency of the transmitter's master clock.
The resonant circuit of the synchronous oscillator (SO) has to be adjusted until it free-runs at 6 MHz. It is important to ensure that the SO oscillates at 6 MHz (i.e. not a harmonic) and the input level potentiometer is set to the minimum input level which permits reliable operation.
The gain and comparator reference point potentiometer should be adjusted such that the phase detector recovers the diphase data steam with HC logic compatible levels.
The VCXO frequency is slowly adjusted until the sliding correlator and delay locked loop lock to and track the transmitter. If a spectrum analyzer is available, a narrowband de-spread BPSK data signal can be detected at the input to the PIF-70 filter. A dual channel oscilloscope can be used to monitor and compare the transmitter and receiver (punctual) PN codes. If the receiver has synchronized then the two PN codes will line up and the receiver code will be seen to track the transmitter's code. If all is correctly adjusted then the synchronous oscillator will regenerate the 6 MHz carrier with the data recovery circuit and delta-modu-delta-modulator IC recovering the audio. Various waveforms are shown on the circuit diagram to aid trouble-shooting.
After this initial procedure the power and pre-amplifiers can be added to free-space checks (provided radio regulations permit). Some minor adjustments particularly of the VCXO frequency may be required to ensure reliable acquisition and locking. If the VCXO frequency offset is too great then the receiver will initially acquire the signal, but will be unable to track it. A degree of trial and error may be necessary to arrive at a receiver clock offset which provides rapid synchronization and reliable tracking performance. The prototype took less than two seconds from power-up to synchronize and would remain in lock provided the signal was not lost.
The Radiocommunications Agency (the UK radio regualtory authority) granted special authority to the author to experiment with spread spectrum techniques on the 70 cm band under his amateur radio service license.
At present the UK amateur radio license does not permit the use of spread spectrum modulation. It is hoped that in the future the standard UK license will permit spread spectrum modules of operation as is allowed in the US by the Federal Communications Commission.
Return to Table of Contents for this issue
In October 2000, this website and the copyright to all editions of
Spread Spectrum Scene Online was purchased by
SSS Online, Inc., and is operated by
Pegasus Technologies. For more of the best information
on RF, Spread Spectrum and wireless, press one of the buttons below: